--Deszyfrowanie
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity decryption is
    Port ( cipher : in  STD_LOGIC_VECTOR (127 downto 0);
		key : in STD_LOGIC_VECTOR (255 downto 0);
		plain_txt : out  STD_LOGIC_VECTOR (127 downto 0));
end decryption;

architecture Behavioral of decryption is

component initialtransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component initialtransf;

component finaltransf is
    Port ( i : in  STD_LOGIC_VECTOR (127 downto 0);
		o : out  STD_LOGIC_VECTOR (127 downto 0));
end component finaltransf;

component invrunda32 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		rdk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda32;

component invrunda1 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda1;

component invrunda2 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda2;

component invrunda3 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda3;

component invrunda4 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda4;

component invrunda5 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
	rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda5;

component invrunda6 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
	rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda6;

component invrunda7 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
	rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda7;

component invrunda8 is
    Port ( ri : in  STD_LOGIC_VECTOR (127 downto 0);
		rk: in STD_LOGIC_VECTOR (127 downto 0);
		ro : out  STD_LOGIC_VECTOR (127 downto 0));
end component invrunda8;

component key_schedule is
    Port ( user_key : in  STD_LOGIC_VECTOR (255 downto 0);
		k0 : out  STD_LOGIC_VECTOR (127 downto 0);
		k1 : out  STD_LOGIC_VECTOR (127 downto 0);
		k2 : out  STD_LOGIC_VECTOR (127 downto 0);
		k3 : out  STD_LOGIC_VECTOR (127 downto 0);
		k4 : out  STD_LOGIC_VECTOR (127 downto 0);
		k5 : out  STD_LOGIC_VECTOR (127 downto 0);
		k6 : out  STD_LOGIC_VECTOR (127 downto 0);
		k7 : out  STD_LOGIC_VECTOR (127 downto 0);
		k8 : out  STD_LOGIC_VECTOR (127 downto 0);
		k9 : out  STD_LOGIC_VECTOR (127 downto 0);
		k10 : out  STD_LOGIC_VECTOR (127 downto 0);
		k11 : out  STD_LOGIC_VECTOR (127 downto 0);
		k12 : out  STD_LOGIC_VECTOR (127 downto 0);
		k13 : out  STD_LOGIC_VECTOR (127 downto 0);
		k14 : out  STD_LOGIC_VECTOR (127 downto 0);
		k15 : out  STD_LOGIC_VECTOR (127 downto 0);
		k16 : out  STD_LOGIC_VECTOR (127 downto 0);
		k17 : out  STD_LOGIC_VECTOR (127 downto 0);
		k18 : out  STD_LOGIC_VECTOR (127 downto 0);
		k19 : out  STD_LOGIC_VECTOR (127 downto 0);
		k20 : out  STD_LOGIC_VECTOR (127 downto 0);
		k21 : out  STD_LOGIC_VECTOR (127 downto 0);
		k22 : out  STD_LOGIC_VECTOR (127 downto 0);
		k23 : out  STD_LOGIC_VECTOR (127 downto 0);
		k24 : out  STD_LOGIC_VECTOR (127 downto 0);
		k25 : out  STD_LOGIC_VECTOR (127 downto 0);
		k26 : out  STD_LOGIC_VECTOR (127 downto 0);
		k27 : out  STD_LOGIC_VECTOR (127 downto 0);
		k28 : out  STD_LOGIC_VECTOR (127 downto 0);
		k29 : out  STD_LOGIC_VECTOR (127 downto 0);
		k30 : out  STD_LOGIC_VECTOR (127 downto 0);
		k31 : out  STD_LOGIC_VECTOR (127 downto 0);
		k32 : out  STD_LOGIC_VECTOR (127 downto 0));
end component key_schedule;		 

signal n1, n0, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, Kl0, Kl1, Kl2, Kl3, Kl4, Kl5, Kl6, Kl7, Kl8, Kl9, Kl10, Kl11, Kl12, Kl13, Kl14, Kl15, Kl16, Kl17, Kl18, Kl19, Kl20, Kl21, Kl22, Kl23, Kl24, Kl25, Kl26, Kl27, Kl28, Kl29, Kl30, Kl31, Kl32 : STD_LOGIC_VECTOR (127 downto 0);

begin

--szykowanie kluczy
klucze: key_schedule port map (key, KL0, KL1, KL2, KL3, KL4, KL5, KL6, KL7, KL8, KL9, KL10, KL11, KL12, KL13, KL14, KL15, KL16, KL17, KL18, KL19, KL20, KL21, KL22, KL23, KL24, KL25, KL26, KL27, KL28, KL29, KL30, KL31, KL32);
--poczatkowa permutacja
inperm: initialtransf port map (cipher, n1);
--runda 0
r0: invrunda32 port map (n1, KL31, KL32, n2) ;
--rundy 1-31
r1: invrunda7 port map (n2, KL30, n3);
r2: invrunda6 port map (n3, KL29, n4);
r3: invrunda5 port map (n4, KL28, n5);
r4: invrunda4 port map (n5, KL27, n6);
r5: invrunda3 port map (n6, KL26, n7);
r6: invrunda2 port map (n7, KL25, n8);
r7: invrunda1 port map (n8, KL24, n9);
r8: invrunda8 port map (n9, KL23, n10);
r9: invrunda7 port map (n10, KL22, n11);
r10: invrunda6 port map (n11, KL21, n12);
r11: invrunda5 port map (n12, KL20, n13);
r12: invrunda4 port map (n13, KL19, n14);
r13: invrunda3 port map (n14, KL18, n15);
r14: invrunda2 port map (n15, KL17, n16);
r15: invrunda1 port map (n16, KL16, n17);
r16: invrunda8 port map (n17, KL15, n18);
r17: invrunda7 port map (n18, KL14, n19);
r18: invrunda6 port map (n19, KL13, n20);
r19: invrunda5 port map (n20, KL12, n21);
r20: invrunda4 port map (n21, KL11, n22);
r21: invrunda3 port map (n22, KL10, n23);
r22: invrunda2 port map (n23, KL9, n24);
r23: invrunda1 port map (n24, KL8, n25);
r24: invrunda8 port map (n25, KL7, n26);
r25: invrunda7 port map (n26, KL6, n27);
r26: invrunda6 port map (n27, KL5, n28);
r27: invrunda5 port map (n28, KL4, n29);
r28: invrunda4 port map (n29, KL3, n30);
r29: invrunda3 port map (n30, KL2, n31);
r30: invrunda2 port map (n31, KL1, n32);
r31: invrunda1 port map (n32, KL0, n0);
--final transformation
finperm: finaltransf port map (n0,plain_txt);

end Behavioral;